The present invention relates to a method and/or architecture for programmable logic devices generally and, more particularly, to a method and/or architecture for a programmable number of metal lines and effective metal width along a critical path in a programmable logic device.
Referring to FIG. 1, a chart 10 illustrating a comparison between sources of delay in an integrated circuit (IC) is shown. The chart 10 is shown comprising three traces. A trace 12 illustrates overall device delay. A trace 14 illustrates a portion of the overall device delay from gate delay. A trace 16 illustrates a portion of the overall device delay from interconnect delay. Currently, gate delays are larger than interconnect delays as shown by a portion 18. For example, at a technology generation of 500 nm, the gate delay contribution is 4 times the interconnect delay as shown by a point 20. As technology generations decrease the scale of integrated circuits, gate delays and interconnect delays will, at some point, contribute equally to overall delay as shown by a point 22. However, as the technology generations continue to shrink the distances in ICs, the interconnect delays will become more of a concern than the gate delays as shown by a portion 24. For example, when the technology generation reaches 180 nm, the delay due to the gates will be only four-tenths the delay due to the interconnects as shown by a point 26.
The delay due to interconnects is of particular concern in a critical path of an integrated circuit. For best performance, the width of the metal lines along a critical path may need to change depending on the characteristics of the critical path. For example, in a microprocessor, a critical path signal is carried by a dedicated metal bus. The critical path of the microprocessor does not change. The metal width and parasitics of the metal bus can be optimized to meet performance requirements.
A programmable logic device (PLD) allows programmable logic to be implemented in an integrated circuit. Like most other ICs, a PLD has critical speed paths. However, the critical speed paths change depending upon the particular logic function implemented. In conventional PLDs, a critical path signal is carried by a single metal line. The particular metal line may be chosen from an array of metal lines depending on the logic function being implemented. Conventional PLDs have fixed metal line widths along the paths in the PLD. Area considerations prevent optimizing the widths of the metal lines to improve performance. The metal line width cannot be changed and optimized for a particular critical path.
Some characteristics of conventional PLDs have been optimized. For example, some software can choose more than one line (e.g., two lines), usually running in different directions, for load distribution.
As technology generations lead to interconnect delays dominating gate delays, a PLD architecture and/or programming software that may actively minimize interconnect delays is needed.
The present invention concerns a layout architecture for a programmable logic device comprising one or more adjacent metal lines, a first circuit, and a second circuit. The one or more adjacent metal lines may each comprise a critical path. The first circuit may be configured to present an input signal to each of the one or more adjacent metal lines in response to a configuration signal. The second circuit may be configured to (i) receive a signal from at least one of the-one or more adjacent metal lines selected in response to the configuration signal and (ii) generate an output signal in response to the received signal.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) minimize parasitics along a critical path, (ii) increase performance of a critical path, (iii) use a number of adjacent metal lines for a critical path, and/or (iv) provide a programmable effective metal width of a critical path.